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DATA SHEET
MOS INTEGRATED CIRCUIT
PD784224, 784225, 784224Y, 784225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
The PD784224 and 784225 are products of the PD784225 Subseries in the 78K/IV Series. Besides a highspeed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware. The PD784224Y and 784225Y are based on the PD784225 Subseries with the addition of a multimastersupporting I2C bus interface. Flash memory versions, the PD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM version with flash memory, and various development tools are also available. The functions are explained in detail in the following user's manuals. Be sure to read this manual when designing your system.
PD784225, 784225Y Subseries User's Manual - Hardware : U12697E
78K/IV Series User's Manual - Instruction : U10905E
FEATURES
* I2C bus * ROM correction * Inherits peripheral functions of PD780058Y Subseries * Minimum instruction execution time 160 ns (main system clock fXX = 12.5 MHz) 61 s (subsystem clock fXT = 32.768 kHz) * I/O port: 67 pins * Timer/counter: 16-bit timer/counter x 1 unit 8-bit timer/counter x 4 units * Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, multi-master supporting busNote): 1 channel Note PD784225Y Subseries only I 2C * Standby function HALT/STOP/IDLE mode In power-saving mode: HALT/IDLE mode (with subsystem clock) * Clock division function * Watch timer: 1 channel * Watchdog timer: 1 channel * Clock output function fXX, fXX/2, fXX/22, fXX/23 , fXX/24, fXX/25, fXX/26, fXX/27 , fXT selectable * Buzzer output function fXX/210, fXX/211, fXX/212, fXX/213 selectable * A/D converter: 8-bit resolution x 8 channels * D/A converter: 8-bit resolution x 2 channels * Supply voltage: VDD = 1.8 to 5.5 V
APPLICATION FIELD
Car audio, portable audio, telephones, etc. Unless contextually excluded, references in this document to PD784225 mean PD784224, 784225, 784224Y, and 784225Y.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Document No. U12376EJ1V0DS00 (1st edition) Date Published May 2000 J CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997, 2000
PD784224, 784225, 784224Y, 784225Y
ORDERING INFORMATION
Part Number Package 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic plastic plastic plastic QFP (14 x 14 mm) TQFP (fine pitch) (14 QFP (14 x 14 mm) TQFP (fine pitch) (14 QFP (14 x 14 mm) TQFP (fine pitch) (14 QFP (14 x 14 mm) TQFP (fine pitch) (14 x 20 mm) x 20 mm) x 20 mm) x 20 mm) Internal ROM (Bytes) Internal RAM (Bytes) 96 K 96 K 128 K 128 K 96 K 96 K 128 K 128 K 3,584 3,584 4,352 4,352 3,584 3,584 4,352 4,352
PD784224GC-xxx-8BT PD784224GK-xxx-9EUNote PD784225GC-xxx-8BT PD784225GK-xxx-9EU PD784224YGC-xxx-8BT PD784224YGK-xxx-9EU PD784225YGC-xxx-8BTNote PD784225YGK-xxx-9EUNote
Note Under development Remark xxx indicates a ROM code suffix.
2
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
78K/IV SERIES LINEUP
: In mass production : Under development Supports I2C bus Supports multi-master I2C bus
PD784038Y PD784038
PD784225Y PD784225
80-pin, ROM correction added Supports multi-master I2C bus
Standard models
PD784026
Enhanced A/D converter, 16-bit timer, and power management
Enhanced internal memory capacity Pin-compatible with the PD784026 Supports multi-master I2C bus
PD784216AY PD784216A
100-pin, enhanced I/O and internal memory capacity
PD784218AY PD784218A
Enhanced internal memory capacity, ROM correction added
PD784054 PD784046
ASSP models
PD784956A
For DC inverter control
On-chip 10-bit A/D converter
PD784938A
Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added. Supports multi-master I2C bus
PD784908
On-chip IEBusTM controller
PD784928Y PD784915
Software servo control On-chip analog circuit for VCRs Enhanced timer
PD784928
Enhanced functions of the PD784915
PD784967
On-chip FIP controller/driver
Data Sheet U12376EJ1V0DS00
3
PD784224, 784225, 784224Y, 784225Y
FUNCTIONS
Part Number Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O port Total CMOS Input CMOS I/O Pins with ancillary Pins with pull-up resistor ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) * 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: fXX = 12.5 MHz) * 61 s (subsystem clock: fXT = 32.768 kHz) 96 Kbytes 3,584 bytes 67 8 59 57 16 4 bits x 2, or 8 bits x 1 Timer/event counter (16-bit) : Timer counter x 1 Capture/compare register x 2 Pulse output * PWM/PPG output * Square wave output * One-shot pulse output Pulse output * PWM output * Square wave output Pulse output * PWM output * Square wave output 128 Kbytes 4,352 bytes
PD784224, PD784224Y
PD784225, PD784225Y
1 MB with program and data spaces combined
functionsNote 1 LEDs direct drive output Real-time output port Timer
Timer/event counter 1 : Timer counter x 1 (8-bit) Compare register x 1 Timer/event counter 2 : Timer counter x 1 (8-bit) Compare register x 1 Timer 5 (8-bit) Timer 6 (8-bit) Serial interface A/D converter D/A converter Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware Software Non-maskable Maskable : Timer counter x 1 Compare register x 1 : Timer counter x 1 Compare register x 1
* UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) * CSI (3-wire serial I/O, I2C busNote 2 supporting multi master): 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25 , fXX/26 , fXX/27, fXT Selectable from fXX/210, fXX/211, fXX/212, fXX/213 1 channel 1 channel * HALT/STOP/IDLE mode * In power-saving mode (with subsystem clock): HALT/IDLE mode 25 (internal: 18, external: 7) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 17, external: 6 * 4 programmable priority levels * 3 service modes: vectored interrupt/macro service/context switching
Supply voltage Package
VDD = 1.8 to 5.5 V * 80-pin plastic QFP(14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Notes 1. The pins with ancillary functions are included in the I/O pins. 2. PD784225Y Subseries only
4
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
CONTENTS
1. 2.
DIFFERENCES AMONG MODELS IN PD784225, 784225Y SUBSERIES .............................. 7 MAJOR DIFFERENCES BETWEEN PD784216Y SUBSERIES AND PD780058Y SUBSERIES ............................................................................................................. 8 PIN CONFIGURATION (Top View) ............................................................................................... 9 BLOCK DIAGRAM ........................................................................................................................ 11 PIN FUNCTION ............................................................................................................................... 12
5.1 5.2 5.3 Port Pins ................................................................................................................................................ 12 Pins Other Than Port Pins .................................................................................................................. 14 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16
3. 4. 5.
6.
CPU ARCHITECTURE ................................................................................................................... 20
6.1 6.2 Memory Space ...................................................................................................................................... 20 CPU Registers ...................................................................................................................................... 23 6.2.1 6.2.2 6.2.3 General-purpose registers .......................................................................................................... 23 Control registers .......................................................................................................................... 24 Special function registers (SFRs) ............................................................................................... 25
7.
PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30
7.1 7.2 7.3 7.4 7.5 7.6 7.7 Ports ....................................................................................................................................................... 30 Clock Generator ................................................................................................................................... 31 Real-Time Output Port ......................................................................................................................... 33 Timer ...................................................................................................................................................... 34 A/D Converter ....................................................................................................................................... 37 D/A Converter ....................................................................................................................................... 38 Serial Interface ..................................................................................................................................... 39 7.7.1 7.7.2 7.8 7.9 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40 Clocked serial interface (CSI) ..................................................................................................... 42
Clock Output Function ........................................................................................................................ 43 Buzzer Output Function ...................................................................................................................... 44
7.10 Edge Detection Function .................................................................................................................... 44 7.11 Watch Timer .......................................................................................................................................... 44 7.12 Watchdog Timer ................................................................................................................................... 45
8.
INTERRUPT FUNCTION ................................................................................................................ 46
8.1 8.2 8.3 8.4 8.5 Interrupt Sources ................................................................................................................................. 46 Vectored Interrupt ................................................................................................................................ 48 Context Switching ................................................................................................................................ 49 Macro Service ....................................................................................................................................... 49 Application Example of Macro Service ............................................................................................. 50
Data Sheet U12376EJ1V0DS00
5
PD784224, 784225, 784224Y, 784225Y
9. LOCAL BUS INTERFACE ............................................................................................................. 51
9.1 9.2 9.3 Memory Expansion .............................................................................................................................. 51 Programmable Wait ............................................................................................................................. 51 External Access Status Function ...................................................................................................... 51
10. STANDBY FUNCTION ................................................................................................................... 52 11. RESET FUNCTION ......................................................................................................................... 54 12. ROM CORRECTION ...................................................................................................................... 55 13. INSTRUCTION SET ........................................................................................................................ 56 14. ELECTRICAL SPECIFICATIONS ................................................................................................. 61 15. PACKAGE DRAWINGS ................................................................................................................. 82 16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 84 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 85 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 88
6
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
1. DIFFERENCES AMONG MODELS IN PD784225, 784225Y SUBSERIES
The only difference among the PD784224 and 784225 lies in the internal memory capacity. The PD784224Y and 784225Y are based on the PD784224 and 784225 respectively, with the addition of an I2C bus control function. The PD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences among Models in PD784225, 784225Y Subseries
Part Number Item Internal ROM
PD784224, PD784224Y
96 Kbytes (mask ROM) 3,584 bytes
PD784225, PD784225Y
128 Kbytes (mask ROM) 4,352 bytes
PD78F4225, PD78F4225Y
128 Kbytes (Flash memory)
Internal RAM
Internal memory None size switching register (IMS)Note Supply voltage Electrical specifications Recommended soldering conditions TEST pin VPP pin Provided None VDD = 1.8 to 5.5 V Refer to the data sheet for each device.
Provided
VDD = 1.9 to 5.5 V
None Provided
Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.
Data Sheet U12376EJ1V0DS00
7
PD784224, 784225, 784224Y, 784225Y
2. MAJOR DIFFERENCES BETWEEN PD784216Y SUBSERIES AND PD780058Y SUBSERIES
Series Name Item CPU Minimum instruction execution time With main system clock selected With subsystem clock
PD784225, 784225Y Subseries
16-bit CPU 160 ns (at 12.5 MHz) 61 s (at 32.768 kHz)
PD784216Y Subseries
PD780058Y Subseries
8-bit CPU 400 ns (at 5.0 MHz) 122 s (at 32.768 kHz)
Memory space I/O port Total CMOS input CMOS I/O N-ch open-drain I/O Pins with ancillary functionNote 1 Pins with pull-up resistor LED direct drive output Medium-voltage pin Timer/counter
1 Mbytes 67 pins 8 pins 59 pins - 57 pins 86 pins 8 pins 72 pins 6 pins 70 pins
64 Kbytes 68 pins 2 pins 62 pins 4 pins 66 pins (flash memory model: 62 pins) 12 pins
16 pins - * 16-bit timer/event counter x 1 unit * 8-bit timer/event counter x 4 units
22 pins
6 pins * 16-bit timer/event counter x 1 unit * 8-bit timer/event counter x 6 units
4 pins * 16-bit timer/event counter x 1 unit * 8-bit timer/event counter x 2 units * UART (time-division transfer function)/IOE (3-wire serial I/O) x 2 channels * CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) x 1 channel * CSI (3-wire serial I/O with automatic transmission/reception function) x 1 channel None None None 2 levels HALT/STOP mode
Serial interface
* UART/IOE (3-wire serial I/O) x 2 channels * CSI (3-wire serial I/O, multi-master supporting I2C busNote 2) x 1 channel
Interrupt
NMI pin Macro service Context switching
Provided Provided Provided
Programmable priority 4 levels Standby function * HALT/STOP/IDLE mode * Power-saving mode: HALT/IDLE Mode Provided * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) None * 100-pin plastic QFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm)
ROM correction Package
Provided * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Notes 1. Pins with ancillary function are included in the I/O pins. 2. PD784225Y and 784216Y Subseries only
8
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
3. PIN CONFIGURATION (Top View)
* 80-pin plastic QFP (14 x 14 mm)
PD784224GC-xxx-8BT, PD784224YGC-xxx-8BT, PD784225GC-xxx-8BT, PD784225YGC-xxx-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD784224GK-xxx-BE9, PD784224YGK-xxx-BE9, PD784225GK-xxx-BE9, PD784225YGK-xxx-BE9
P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2/NMI P01/INTP1 P00/INTP0
XT1 XT2 TESTNote 2
A14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVDD
X1 X2 VDD1
VDD0
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD2 P71/SO2/TxD2 P72/SCK2/ASCK2 P20/SI1/RxD1 P21/SO1/TxD1 P22/SCK1/ASCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 1 P26/SO0 P27/SCK0/SCL0Note 1 P40/AD0 P41/AD1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS0
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS1
Notes 1. The SCL0 and SDA0 pins are available in PD784225Y Subseries only. 2. Connect the TEST pin to VSS0 directly or via a pull-down resistor. For the pull-down connection, use of a resistor with a resistance ranging from 470 to 10 k is recommended. Caution Connect the AVSS pin to VSS0. Remark When using in applications where noise from inside the microcomputer has to be reduced, it is recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1 independently, and connecting VSS0 and VSS1 to different ground lines.
Data Sheet U12376EJ1V0DS00
P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD
9
PD784224, 784225, 784224Y, 784225Y
A8 to A19 AD0 to AD7 ANI0 to ANI7 ANO0, ANO1 ASCK1, ASCK2 ASTB AVDD AVREF1 AVSS BUZ EXA INTP0 to INTP5 NMI P00 to P05 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 : Address Bus : Address/Data Bus : Analog Input : Analog Output : Asynchronous Serial Clock : Address Strobe : Analog Power Supply : Analog Reference Voltage : Analog Ground : Buzzer Clock : External Access Status Output : Interrupt from Peripherals : Non-maskable Interrupt : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port12 P130, P131 PCL RD RESET RTP0 to RTP7 RxD1, RxD2 SCK0 to SCK2 SCL0Note SDA0 Note SI0 to SI2 SO0 to SO2 TEST TO0 to TO2 TxD1, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2 XT1, XT2 : Port13 : Programmable Clock : Read Strobe : Reset : Real-time Output Port : Receive Data : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Output : Test : Timer Output : Transmit Data : Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
TI00, TI01, TI1, TI2 : Timer Input
Note The SCL0 and SDA0 pins are available in PD784225Y Subseries only.
10
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
4. BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 to INTP5 TI00 TI01 TO0 TI1 TO1 TI2 TO2 PROGRAMMABLE INTERRUPT CONTROLLER TIMER/EVENT COUNTER (16 BITS) TIMER/EVENT COUNTER1 (8 BITS) TIMER/EVENT COUNTER2 (8 BITS) TIMER/COUNTER5 (8 BITS) 78K/IV CPU CORE TIMER/COUNTER6 (8 BITS) PORT0 WATCH TIMER PORT1 PORT2 WATCHDOG TIMER RAM RTP0 to RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS ANI0 to ANI7 AVDD AVSS P03/INTP3 REAL-TIME OUTPUT PORT PORT3 PORT4 PORT5 PORT6 D/A CONVERTER PORT7 PORT12 A/D CONVERTER PORT13 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130, P131 RESET CLOCK OUTPUT CONTROL X1 SYSTEM CONTROL X2 XT1 BUZ BUZZER OUTPUT XT2 VDD0, VDD1 VSS0, VSS1 TEST P10 to P17 P20 to P27 ROM BUS I/F UART/IOE1 BAUD-RATE GENERATOR UART/IOE2 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note SO0 SCK0/SCL0Note AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT ASTB EXA P00 to P05
PCL
Note This function supports the I2C bus interface and is available in PD784225Y Subseries only. Remark The internal ROM and RAM capacities differ depending on the model.
Data Sheet U12376EJ1V0DS00
11
PD784224, 784225, 784224Y, 784225Y
5. PIN FUNCTION 5.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P10 to P17 Input I/O I/O Alternate Function INTP0 INTP1 INTP2/NM1 INTP3 INTP4 INTP5 ANI0 to ANI7 Port 1 (P1): * 8-bit input port Port 2 (P2): * 8-bit I/O port * Can be set in input or output mode bit-wise. * Pins set in input mode can be connected to internal pull-up resistors by software bit-wise. Function Port 0 (P0): * 6-bit I/O port * Can be set in input or output mode bit-wise. * Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
I/O
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 PCL BUZ SI0/SDA0Note SO0 SCK0/SCL0Note
I/O
TO0 TO1 TO2 TI1 TI2 TI00 TI01 EXA
Port 3 (P3): * 8-bit I/O port * Can be set in input or output mode bit-wise. * Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.
I/O
AD0 to AD7
Port 4 (P4): * 8-bit I/O port * Can be set in input or output mode bit-wise. * All pins set in input mode can be connected to internal pull-up resistors by software. * Can drive LEDs. Port 5 (P5): * 8-bit I/O port * Can be set in input or output mode bit-wise. * All pins set in input mode can be connected to internal pull-up resistors by software. * Can drive LEDs.
P50 to P57
I/O
A8 to A15
Note This function is available in PD784255Y Subseries only.
12
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
5.1 Port Pins (2/2)
Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 I/O I/O I/O Alternate Function A16 A17 A18 A19 RD WR WAIT ASTB RxD2/SI2 Port 7 (P7): * 3-bit I/O port * Can be set in input or output mode bit-wise. * Pins set in input mode can be connected to internal pull-up resistor by software bit-wise. Function Port 6 (P6): * 8-bit I/O port * Can be set in input or output mode bit-wise. * All pins set in input mode can be connected to internal pull-up resistors by software.
P71
TxD2/SO2
P72
ASCK2/SCK2
P120 to P127
I/O
RTP0 to RTP7
Port 12 (P12): * 8-bit I/O port * Can be set in input or output mode bit-wise. * Pins set in input mode can be connected to internal pull-up resistor by software bit-wise. Port 13 (P13): * 2-bit I/O port * Can be set in input or output mode bit-wise.
P130, P131
I/O
ANO0, ANO1
Data Sheet U12376EJ1V0DS00
13
PD784224, 784225, 784224Y, 784225Y
5.2 Pins Other Than Port Pins (1/2)
Pin Name TI00 TI01 TI1 TI2 TO0 TO1 TO2 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SI0 SI1 SI2 SO0 SO1 SO2 SDA0Note SCK0 SCK1 SCK2 SCL0Note NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 PCL BUZ RTP0 to RTP7 Output Output Output Input I/O I/O Output Input Intput Output Input Output I/O Input Alternate Function P35 P36 P33 P34 P30 P31 P32 P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0Note P20/RxD1 P70/RxD2 P26 P21/TxD1 P71/TxD2 P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P00 P01 P02/NMI P03 P04 P05 P23 P24 P120 to P127 Clock output (for trimming main system clock and subsystem clock) Buzzer output Real-time output port that outputs data in synchronization with trigger Low-order address/data bus when external memory is connected Middle-order address bus when external memory is connected High-order address bus when external memory is connected Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial clock I/O0) Serial data input (3-wire serial clock I/O1) Serial data input (3-wire serial clock I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data input/output (I2C bus) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (I2C bus) Non-maskable interrupt request input External interrupt request input Function External count clock input to 16-bit timer register Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer register 1 External count clock input to 8-bit timer register 2 16-bit timer output (shared by 14-bit PWM output) 8-bit timer output (shared by 8-bit PWM output)
AD0 to AD7 A8 to A15 A16 to A19
I/O Output
P40 to P47 P50 to P57 P60 to P63
Note This function is available in PD784255Y Subseries only.
14
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
5.2 Pins Other Than Port Pins (2/2)
Pin Name RD WR WAIT ASTB Input Output I/O Output Alternate Function P64 P65 P66 P67 Function Strobe signal output for read operation of external memory Strobe signal output for write operation of external memory To insert wait state(s) when external memory is accessed Strobe output to externally latch address information output to ports 4 to 6 to access external memory External access status output - - System reset input To connect main system clock oscillation crystal
EXA RESET X1 X2 XT1 XT2 ANI0 to ANI7 ANO0, ANO1 AVREF1 AVDD AVSS VDD0 VSS0 VDD1 VSS1 TEST
Output Input Input - Input - Input Output -
P37
-
To connect subsystem clock oscillation crystal
P10 to P17 P130, P131 -
Analog voltage input for A/D converter Analog voltage output for D/A converter To apply reference voltage for D/A converter Positive power supply for A/D converter. Connected to VDD0. GND for A/D converter and D/A converter. Connected to VSS0. Positive power supply for port block GND potential for port block Positive power supply (except port block) GND potential (except port block) Connect this pin to VSS0 directly or via pull-down resistor. For the pull-down connection, use of a resistor with a resistance ranging from 470 to 10 k is recommended.
Data Sheet U12376EJ1V0DS00
15
PD784224, 784225, 784224Y, 784225Y
5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection of unused pins. For the circuit diagram of each type of I/O circuit, refer to Figure 5-1. Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)
Pin Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 to P05/INTP5 P10/ANI0 to P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SDA0Note/SI0 P26/SO0 P27/SCL0Note/SCK0 P30/TO0 to P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 8-K 8-L 8-K 10-I 10-J 10-I 8-M 8-K 8-L 8-M 5-H 9 10-I 10-J 10-I 10-J Input I/O Connected to VSS0 or VDD0 Input : Individually connected to VSS0 via resistor Output: Open I/O Circuit Type 8-K I/O I/O Recommended Connections of Unused Pins Input : Individually connected to VSS0 via resistor Output: Open
Note This function is available in PD784255Y Subseries only. Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).
16
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)
Pin Name P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET XT1 XT2 AVREF1 AVDD AVSS TEST/VPPNote Connected to VSS0 Directly connected to VSS0 - I/O Circuit Type 8-K 12-D 2-G 16 - Input Connected to VSS0 Open Connected to VDD0 I/O I/O Recommended Connections of Unused Pins Input : Individually connected to VSS0 via resistor Output: Open -
Note VPP pin is available in PD78F4225, 78F4255Y only. Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).
Data Sheet U12376EJ1V0DS00
17
PD784224, 784225, 784224Y, 784225Y
Figure 5-1. Types of Pin I/O Circuits (1/2)
Type 2-G
Type 8-M
VDD0
pullup enable VDD0 IN data P-ch
P-ch
IN/OUT Schmitt trigger input with hysteresis characteristics output disable VSS0 input enable Type 5-H pullup enable VDD0 data P-ch IN/OUT output disable VSS0 input enable Type 8-K VDD0 Type 10-I VDD0 N-ch input enable VDD0 Type 9 N-ch
P-ch IN P-ch N-ch Comparator
+ -
VREF (threshold voltage)
pullup enable VDD0 data P-ch
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
IN/OUT open drain output disable VSS0 N-ch
output disable VSS0
N-ch
Type 8-L
VDD0
Type 10-J
VDD0
pullup enable VDD0 data P-ch
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
IN/OUT open drain output disable VSS0 N-ch
open drain output disable VSS0
N-ch
18
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Figure 5-1. Types of Pin I/O Circuits (2/2)
Type 12-D
VDD0 data P-ch IN/OUT output disable input enable N-ch VSS0 P-ch Analog output voltage
N-ch
VSS0
Type 16 feedback cut-off P-ch
XT1
XT2
Data Sheet U12376EJ1V0DS00
19
PD784224, 784225, 784224Y, 784225Y
6. CPU ARCHITECTURE 6.1 Memory Space
A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once. (1) When LOCATION 0H instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows:
Part Number Internal Data Area 0F100H to 0FFFFH Internal ROM Area 00000H to 0F0FFH 10000H to 17FFFH 00000H to 0EDFFH 10000H to 1FFFFH
PD784224, PD784224Y PD784225, PD784225Y
0EE00H to 0FFFFH
Caution
The following areas that overlap the internal data area of the internal ROM cannot be used when the LOCATION 0H instruction is executed.
Part Number Unusable Area 0F100H to 0FFFFH (3,840 bytes)
PD784224, PD784224Y PD784225, PD784225Y
0EE00H to 0FFFFH (4,608 bytes)
* External memory The external memory is accessed in external memory expansion mode. (2) When LOCATION 0FH instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows:
Part Number Internal Data Area FF100H to FFFFFH Internal ROM Area 00000H to 17FFFH
PD784224, PD784224Y PD784225, PD784225Y
FEE00H to FFFFFH
00000H to 1FFFFH
* External memory The external memory is accessed in external memory expansion mode.
20
Data Sheet U12376EJ1V0DS00
Figure 6-1. Memory Map of PD784224, 784224Y
On execution of LOCATION 0FH instruction
function registers (SFR) (256 bytes)
On execution of LOCATION 0H instruction
F F F F FH
0 FEF FH
F FEF FH
F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH
External memory (928 Kbytes)
0 FE8 0H 0 FE 7 FH FFE8 0H F FE 7 FH FF 1 0 0H F F 0 F FH
Note 1
General-purpose registers (128 bytes) Internal RAM (3,584 bytes)
1 8 0 0 0H 1 7 F F FH
Internal ROM
0 FE3 9H FFE3 9H FFE0 6H
(SFR)
0 FE0 6H
Macro service control word area (52 bytes) Data area (512 bytes)
(32,768 bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 bytes) 0 FF 0 0H 0 FEF FH
0 FD0 0H 0 FCF FH F FD0 0H F FCF FH
Internal RAM (3,584 bytes) Program/data area (3,072 bytes)
0 F 1 0 0H FF 7 0 0H
External memory (980,736 bytes)
Note 1
0 F 1 0 0H 0 F 0 F FH 1 7 F F FH 1 0 0 0 0H
1 7 F F FH
Note 2
0 F 0 F FH
Data Sheet U12376EJ1V0DS00
Note 4
0 1 0 0 0H 0 0 F F FH
Program/data area CALLF entry area (2 Kbytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H
Note 3
Internal ROM (61,696 bytes)
1 8 0 0 0H 1 7 F F FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (96 Kbytes)
Note 4
0 0 0 0 0H
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
PD784224, 784225, 784224Y, 784225Y
3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes
21
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
22
Figure 6-2. Memory Map of PD784225, 784225Y
On execution of LOCATION 0FH instruction
function registers (SFR) (256 bytes)
Note 1
0 FEF FH F FEF FH F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH
On execution of LOCATION 0H instruction
F F F F FH
External memory (896 Kbytes) General-purpose registers (128 bytes) Internal RAM (4,352 bytes)
FFE8 0H F FE 7 FH FEE 0 0H F EDF FH 0 FE8 0H 0 FE 7 FH
2 0 0 0 0H 1 F F F FH
Internal ROM (65,536 bytes)
0 FE3 9H 0 FE0 6H FFE0 6H FFE3 9H
function registers (SFR) (256 bytes)
Macro service control word area (52 bytes) Data area (512 bytes)
1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH
Internal RAM (4,352 bytes) Program/data area (3,840 bytes)
0 EE 0 0H FEE 0 0H 1 F F F FH
0 FD0 0H 0 FCF FH F FD0 0H F FCF FH
External memory (912,896 bytes)
Note 1
0 EE 0 0H 0 EDF FH 1 F F F FH 1 0 0 0 0H
Note 2
0 EDF FH
Data Sheet U12376EJ1V0DS00
Note 4
0 1 0 0 0H 0 0 F F FH
Program/data area
Note 3
Internal ROM (60,928 bytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H
CALLF entry area (2 Kbytes)
2 0 0 0 0H 1 F F F FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (128 Kbytes)
Note 4
0 0 0 0 0H
0 0 0 0 0H
Notes 1. Accessed in external memory expansion mode.
2. This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes
PD784224, 784225, 784224Y, 784225Y
4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
PD784224, 784225, 784224Y, 784225Y
6.2 CPU Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of these registers are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-3. General-Purpose Register Format
A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U R11 R9 VP (RP4)
X (R0) C (R2) R4 R6 R8
R10
T
UP (RP5) UUP (RG5) D (R13) E (R12) DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) HL (RP7) ) indicate an absolute name.
W
Parentheses (
Caution
Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.
Data Sheet U12376EJ1V0DS00
23
PD784224, 784225, 784224Y, 784225Y
6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-4. Program Counter (PC) Format
19 PC 0
(2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-5. Program Status Word (PSW) Format
15 PSWH PSW 7 PSWL S 6 Z 5 RSS
Note
14 RBS2
13 RBS1
12 RBS0
11 -
10 -
9 -
8 -
UF
4 AC
3 IE
2 P/V
1 0
0 CY
Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-6. Stack Pointer (SP) Format
23 PC 0 0 0 0 20 0
24
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H to 0FFFFHNote. Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the PD784225 may be in the deadlock status. This deadlock status can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: * Symbol ............................... Symbol indicating an SFR. C compiler (CC78K4). * R/W .................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W : Read/write R W : Read-only : Write-only This symbol is reserved for NEC's assembler
(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the
* Bit units for manipulation .. Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. * At reset .............................. Indicates the status of the register when the RESET signal has been input.
Data Sheet U12376EJ1V0DS00
25
PD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (1/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF2CH 0FF2DH 0FF30H 0FF32H 0FF33H 0FF37H 0FF3CH 0FF40H Capture/compare register 00 (16-bit timer/counter) Capture/compare register 01 (16-bit timer/counter) Capture/compare control register 0 16-bit timer mode control register 16-bit timer output control register Prescaler mode register 0 Port 0 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Port 12 mode register Port 13 mode register Pull-up resistor option register 0 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 7 Pull-up resistor option register 12 Clock output control register CRC0 TMC0 TOC0 PRM0 PM0 PM2 PM3 PM4 PM5 PM6 PM7 PM12 PM13 PU0 PU2 PU3 PU7 PU12 CKS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00H FFH 00H CR01 -- -- CR00 R/W -- -- Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 16-bit timer counter P0 P1 P2 P3 P4 P5 P6 P7 P12 P13 TM0 R -- -- R/W R R/W 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- 0000H 00HNote 2 At Reset
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. Because each port is initialized to input mode at reset, "00H" is not actually read. The output latch is initialized to "0".
26
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (2/4)
AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF64H 0FF65H 0FF68H 0FF69H 0FF6CH 0FF6DH 0FF70H 0FF71H 0FF72H 0FF73H 0FF74H Port function control register Pull-up resistor option register 8-bit timer counter 1 8-bit timer counter 2 Compare register 10 (8-bit timer/counter 1) Compare register 20 (8-bit timer/counter 2) 8-bit timer mode control register 1 8-bit timer mode control register 2 Prescaler mode register 1 Prescaler mode register 2 8-bit timer counter 5 8-bit timer counter 6 Compare register 50 (8-bit timer/counter 5) Compare register 60 (8-bit timer/counter 6) 8-bit timer mode control register 5 8-bit timer mode control register 6 Prescaler mode register 5 Prescaler mode register 6 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 Transmit shift register 1 Receive buffer register 1 0FF75H Transmit shift register 2 Receive buffer register 2 0FF76H 0FF77H 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H Baud rate generator control register 1 Baud rate generator control register 2 Oscillation mode select register A/D converter mode register A/D converter input select register A/D conversion result register D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register 0 D/A converter mode register 1 PF2 PUO TM1 TM2 CR10 CR1W CR20 TMC1 TMC1W TMC2 PRM1 PRM1W PRM2 TM5 TM5W R TM6 CR50 CR5W CR60 TMC5 TMC5W TMC6 PRM5 PRM5W PRM6 ASIM1 ASIM2 ASIS1 ASIS2 TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2 CC ADM ADIS ADCR DACS0 DACS1 DAM0 DAM1 R R/W -- W R W R R/W -- -- -- -- R -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Undefined 00H 00H FFH 00H R/W -- -- -- -- R/W TM1W R -- -- -- -- R/W 8 Bits 16 Bits -- -- 0000H 00H At Reset
Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed.
Data Sheet U12376EJ1V0DS00
27
PD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (3/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8DH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H 0FFB6H 0FFB8H 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFC8H 00FFCEH 0FFCFH 0FFD0H to 0FFDFH External access status enable register Serial operation mode register 0 Serial operation mode register 1 Serial operation mode register 2 Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 2 Real-time output buffer register L Real-time output buffer register H Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Interrupt mask flag register 1H I2C bus control registerNote 2 Prescaler mode register for serial clock Slave address register I 2C bus status registerNote 2 EXAE CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WTM EGP0 EGN0 ISPR SNMI IMC MK0L MK0 MK0H MK1L MK1 MK1H IICCL0 SPRM0 SVA0 IICS0 IIC0 STBC WDM MM PWC1 PWC2 PCS OSTS -- W R R/W -- -- -- -- -- R R/W -- -- -- -- -- -- -- -- -- -- -- 30H 00H 20H AAH AAAAH 32H 00H -- 00H R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80H FFFFH 00H ROM correction control register ROM correction address pointer H ROM correction address pointer L CORC CORAH CORAL R/W -- -- -- 8 Bits 16 Bits -- -- 0000H 00H At Reset
Serial shift register Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register 1 Programmable wait control register 2 Clock status register Oscillation stabilization time specification register External SFR area
Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed. 2. PD784225Y Subseries only
Data Sheet U12376EJ1V0DS00
28
PD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (4/4)
AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF9H Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTIIC0/INTCSI0) Interrupt control register (INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTWT) WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 WTIC R/W 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 43H At Reset
Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH instruction is executed.
Data Sheet U12376EJ1V0DS00
29
PD784224, 784225, 784224Y, 784225Y
7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports
The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0, 2 to 7, and 12 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration
Port 5

P50
P00
P57 P60
P05
Port 0
P10 to P17
8
Port 1
Port 6
P67 P70 P72 P120
P20
Port 7
P27 P30
Port 2 Port 3 Port 4
Port 12
P127 P130 P131
Port 13
P37 P40
P47
30
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Table 7-1. Port Functions
Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Can be specified bit-wise -- Can be specified bit-wise Can be specified bit-wise Can be specified in 1-port units
Port 0 Port 1 Port 2 Port 3 Port 4
P00 to P05 P10 to P17 P20 to P27 P30 to P37 P40 to P47
* Can be set in input or output mode bit-wise * Input port * Can be set in input or output mode bit-wise * Can be set in input or output mode bit-wise * Can be set in input or output mode bit-wise * Can directly drive LEDs * Can be set in input or output mode bit-wise * Can directly drive LEDs * Can be set in input or output mode bit-wise * Can be set in input or output mode bit-wise * Can be set in input or output mode bit-wise * Can be set in input or output mode bit-wise
Port 5
P50 to P57
Can be specified in 1-port units
Port 6 Port 7 Port 12 Port 13
P60 to P67 P70 to P72 P120 to P127 P130, P131
Can be specified in 1-port units Can be specified bit-wise Can be specified bit-wise --
7.2 Clock Generator
An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generator
XT1 XT2
Subsystem clock oscillator
fXT
Watch timer, clock output function Prescaler
X2
Main system clock oscillator
fX IDLE controller
Frequency divider fX
Selector
X1
fXX fXX 2
Prescaler
Clock to peripheral hardware
2 STOP and bit 2 (MCK) of the standby control register (STBC) = 1 when the subsystem clock is selected as CPU clock
fXX 22
fXX 23 Selector STOP, IDLE controller HALT controller CPU clock (fCPU)
Internal system clock (fCLK)
Data Sheet U12376EJ1V0DS00
31
PD784224, 784225, 784224Y, 784225Y
Figure 7-3. Example of Using Main System Clock Oscillator (1) Crystal/ceramic oscillation (2) External clock
X2
X2
VSS1
X1 VSS Crystal resorator or ceramic resonator
External clock PD74HCU04
X1
Figure 7-4. Example of Using Subsystem Clock Oscillator (1) Crystal oscillation (2) External clock
32.768 kHz VSS1
VSS XT2 External clock
XT2
XT1
XT1
PD74HCU04
Caution
When using the main system clock and subsystem clock oscillator, wire the dotted portions in Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the potential at the ground point of the capacitor in the oscillator the same as VSS1. Do not ground to a ground pattern through which a high current flows. * Do not extract signals from the oscillator. Note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption.
32
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
7.3 Real-Time Output Port
The real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-time output port. Because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor. Figure 7-5. Block Diagram of Real-Time Output Port
Internal bus Real-time output port control register (RTPC) RTPOE BYTE EXTR
INTP2TRG INTTM1 INTTM2 Output trigger controller
Higher 4 bits of real-time output buffer register (RTBH)
Lower 4 bits of real-time output buffer register (RTBL) Real-time output port mode register (RTPM)
Port 12 output latch
Real-time output port output latch
P127************************************** P120
RTP7************************************** RTP0
RTPOE bit
P12n/RTPn pin output (n = 0 to 7)
P127/************************************** P120/ RTP7 RTP0
Data Sheet U12376EJ1V0DS00
33
PD784224, 784225, 784224Y, 784225Y
7.4 Timer
One unit of 16-bit timers/event counters, two units of timers/event counters, and two 8-bit timers are provided. Because a total of six interrupt requests are supported, these timers/counters and timer can be used as six units of timers/counters. Table 7-2. Operations of Timers
Name Item Count width 8 bits 16 bits Operation mode Interval timer External event counter Function Timer output PPG output PWM output Square wave output One-shot pulse output Pulse width measurement Number of interrupt requests 2 inputs 2 -- -- 1 -- -- 1 1ch 1ch -- 1ch -- 1ch 1ch 1ch 1ch -- -- -- -- -- -- -- 1 1ch -- -- -- -- -- -- -- 1 16-Bit 8-Bit 8-Bit Timer/Event Timer/Event Timer/Event Counter Counter 1 Counter 2 -- 8-Bit Timer 5 8-Bit Timer 6
34
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Figure 7-6. Block Diagram of Timers (1/2) 16-bit timer/event counter
fXX/4 fXX/16 INTTM3
Clear
Selector
16-bit timer counter (TM0)
16
Selector
TI01
Edge detector
INTTM00
16 INTTM01 TI00 Edge detector 16-bit capture/compare register 01 (CR01)
Output controller
16-bit capture/compare register 00 (CR00)
TO0
8-bit timer/event counter 1
fXX/22 fXX/23 Clear
Selector
fXX/2
4
fXX/25 fXX/27 fXX/29 TI1 Edge detector
8-bit timer counter 1 (TM1) 8
OVF Output controller TO1
8-bit compare register 10 (CR10) INTTM2
Selector
INTTM1
8-bit timer/event counter 2
TM1 fXX/22 fXX/23 fXX/24 fXX/2 fXX/2
5 7
Clear
Selector
8-bit timer counter 2 (TM2) 8
OVF Output controller TO2
fXX/29 TI2 Edge detector 8-bit compare register 20 (CR20) INTTM2
Remark OVF: Overflow flag
Data Sheet U12376EJ1V0DS00
35
PD784224, 784225, 784224Y, 784225Y
Figure 7-6. Block Diagram of Timers (2/2) 8-bit timer 5
fXX/22 fXX/23 fXX/24 fXX/25 fXX/27 fXX/29 Clear
Selector
8-bit timer counter 5 (TM5) 8
8-bit compare register 50 (CR50) INTTM6
Selector
INTTM5
8-bit timer 6
TM5 fXX/22 Selector fXX/2
3
Clear
fXX/24 fXX/25 fXX/2
7
8-bit timer counter 6 (TM6) 8
fXX/29
8-bit compare register 60 (CR60)
INTTM6
36
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
7.5 A/D Converter
An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with an A/D converter with a resolution of 8 bits and 8 channels (ANI0 to ANI7). This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D conversion result register (ADCR). The A/D converter can be started in the following two ways: * Hardware start Conversion is started by trigger input (P03). * Software start Conversion is started by setting the A/D converter mode register. One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been completed. When conversion is started by means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (INTAD) is generated. Figure 7-7. Block Diagram of A/D Converter
Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR) Selector Voltage comparator Sample & hold circuit Tap selector AVDD
INTP3/P03
Edge detector
Controller
INTAD
Edge detector
A/D conversion result register (ADCR) INTP3 Internal bus
Data Sheet U12376EJ1V0DS00
37
PD784224, 784225, 784224Y, 784225Y
7.6 D/A Converter
A D/A converter converts an input digital signal into an analog voltage. This microcontroller is provided with a voltage output type D/A converter with a resolution of 8 bits and two channels. The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting DACE0 of the D/A converter mode register 0 (DAM0) and DACE1 of the D/ A converter mode register 1 (DAM1). The D/A converter operates in the following two modes: * Normal mode The converter outputs an analog voltage immediately after it has completed D/A conversion. * Real-time output mode The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A conversion. Figure 7-8. Block Diagram of D/A Converter
DACS0 8 2R ANO0 AVREF1 2R R
Selector R 2R DACS1 2R 8 2R ANO1 2R R
Selector R 2R AVSS
2R
38
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
7.7 Serial Interface
Three independent serial interface channels are provided. * Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 * Clocked serial interface (CSI) x 1 * 3-wire serial I/O (IOE) * I2C bus interface (I2C) (PD784225Y Subseries only) Therefore, communication with an external system and local communication within the system can be simultaneously executed (see Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C
PD784225Y (master) PD4711A
[UART] RxD1 RS-232C driver/receiver TxD1

VDD0 [I C]
2
VDD0
PD780078Y (slave)
SDA SCL
SDA0 SCL0
Port
PD780308Y (slave)
SDA LCD
PD4711A
[UART] RxD2 RS-232C driver/receiver TxD2

SCL
Port
(b) UART + 3-wire serial I/O
PD784225Y (master)
PD4711A
[UART] RxD2 RS-232C driver/receiver TxD2

PD753106 (slave)
[3-wise serial I/O] SI SO SCK Note Port INT
SO1 SI1 SCK1 INTPm Port
Port
Note Handshake line
Data Sheet U12376EJ1V0DS00
39
PD784224, 784225, 784224Y, 784225Y
7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode
Internal bus 8 Receive buffer register 1, 2 (RXB1, RXB2) 8 RxD1, RxD2 TxD1, TxD2 Receive control parity check INTSR1, INTSR2 Transmit control parity addition INTST1, INTST2 Receive shift register 1, 2 (RX1, RX2) Transmit shift register 1, 2 (TXS1, TXS2) 8
Baud rate generator
5-bit counter x 2 Transmit/receive clock generation ASCK1, ASCK2
Selector
fXX to fXX/25
40
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO2). To connect two or more devices, a handshake line is necessary. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode
Internal bus 8 Direction controller 8 SI1, SI2 Serial I/O shift register 1, 2 (SIO1, SIO2)
SO1, SO2 SCK1, SCK2 Serial clock counter Serial clock controller Interrupt generator INTCSI1, INTCSI2 TO2 fXX/8 fXX/16
Selector
Data Sheet U12376EJ1V0DS00
41
PD784224, 784225, 784224Y, 784225Y
7.7.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. (1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the reception status. Figure 7-12. Block Diagram in 3-Wise Serial I/O Mode
Internal bus 8 Direction controller 8 SI0 Serial I/O shift register 0 (SIO0)
SO0 SCK0 Serial clock counter Serial clock controller Interrupt generator INTCSI0
Selector
TO2 fXX/8 fXX/16
(2) I2C (Inter IC) bus mode (supporting multi-master) (PD784225Y Subseries only) This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL0) and serial data bus (SDA0). During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During reception, these data can be automatically detected by hardware.
42
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Figure 7-13. Block Diagram in I2C Bus Mode
Internal bus 8 Direction controller 8 SDA0 Serial I/O shift register 0 (SIO0) Output latch 8 Slave address register (SVA0) Wakeup controller
Start condition/ acknowledge detector Stop condition detector SCL0 Serial clock counter Serial clock controller
Acknowledge generator
Interrupt generator
INTIIC0
Selector
TO2/18 to TO2/68 fXX/24 to fXX/178
7.8 Clock Output Function
Clocks of the following frequencies can be output. * 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz (main system clock: 12.5 MHz) * 32.768 kHz (subsystem clock: 32.768 kHz) Figure 7-14. Block Diagram of Clock Output Function
fXX fXX/2 fXX/22 fXX/24 fXX/25 fXX/26 fXX/27 fXT
Selector
fXX/23
Synchronizer
Output controller
PCL
Data Sheet U12376EJ1V0DS00
43
PD784224, 784225, 784224Y, 784225Y
7.9 Buzzer Output Function
Clocks of the following frequencies can be output as buzzer output. * 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (main system clock: 12.5 MHz) Figure 7-15. Block Diagram of Buzzer Output Function
fXX/210 fXX/211 fXX/212 fXX/213
Selector
Output controller
BUZ
7.10 Edge Detection Function
The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise.
Pin Name NMI INTP0 to INTP5 Detectable Edge Either or both of rising and falling edges Noise Reduction By analog delay --
7.11 Watch Timer
The watch timer has the following functions: * Watch timer * Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by using the 32.768-kHz subsystem clock. (2) Interval timer The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.
44
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Figure 7-16. Block Diagram of Watch Timer
fW 214
Selector
Selector
fXX/27 fXT
Selector
fW
5-bit counter
Prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
INTWT
fW 25
Selector
INTTM3 To 16-bit timer/counter
7.12 Watchdog Timer
A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-17. Block Diagram of Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220
Selector
RUNNote HALT IDLE STOP
fCLK/219 fCLK/217
INTWDT
Note Write 1 to bit 7 (RUN) of the watchdog timer (WDM). Remark fCLK: Internal system clock (fXX to fXX/8)
Data Sheet U12376EJ1V0DS00
45
PD784224, 784225, 784224Y, 784225Y
8. INTERRUPT FUNCTION
As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request
Servicing Mode Vectored interrupt Entity of Servicing Software Servicing Branches and executes servicing routine (servicing is arbitrary). Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary). Firmware Executes data transfer between memory and I/O (servicing is fixed) Contents of PC and PSW Saves to and restores from stack. Saves to or restores from fixed area in register bank
Context switching
Macro service
Retained
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 25 types of sources, execution of the BRK instruction, BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (see Table 8-2).
46
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Table 8-2. Interrupt Sources
Type Software Default Priority -- Source Name BRK instruction BRKCS instruction Operand error Trigger Instruction execution Instruction execution If result of exclusive OR between operands byte and byte is not FFH when MOV STBC, #byte instruction or MOV WDM, #byte instruction, LOCATION instruction is executed Pin input edge detection Overflow of watchdog timer Overflow of watchdog timer Pin input edge detection External Internal Internal External -- Internal/ External -- Macro Service --
Non-maskable Maskable
-- 0 (highest) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NMI INTWDT INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTIIC0Note INTCSI0 INTSER1 INTSR1 INTCSI1 INTST1 INTSER2 INTSR2 INTCSI2 INTST2 INTTM3 INTTM00
End of I2C bus transfer by CSI0 End of 3-wire transfer by CSI0 Occurrence of UART reception error in ASI1 End of UART reception by ASI1 End of 3-wire transfer by CSI1 End of UART transfer by ASI1 Occurrence of UART reception error in ASI2 End of UART reception by ASI2 End of 3-wire transfer by CSI2 End of UART transfer by ASI2 Reference time interval signal from watch timer Signal indicating coincidence between 16-bit timer counter and capture/compare register (CR00) Signal indicating coincidence between 16-bit timer counter and capture/compare register (CR01) Occurrence of coincidence signal of 8-bit timer/counter 1 Occurrence of coincidence signal of 8-bit timer/counter 2 End of conversion by A/D converter Occurrence of coincidence signal of 8-bit timer/counter 5 Occurrence of coincidence signal of 8-bit timer/counter 6 Overflow of watch timer
Internal
16
INTTM01
17 18 19 20 21 22 (lowest)
INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTWT
Note PD784255Y Subseries only Remarks 1. ASI : Asynchronous Serial Interface CSI : Clocked Serial Interface 2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.
Data Sheet U12376EJ1V0DS00
47
PD784224, 784225, 784224Y, 784225Y
8.2 Vectored Interrupt
Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: * On branching: Saves the status of the CPU (contents of PC and PSW) to stack * On returning : Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address
Interrupt Source BRK instruction Operand error NMI INTWDT (non-maskable) INTWDTM (maskable) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTIIC0 INTCSI0 INTSER1 INTSR1 INTCSI1 0018H 001AH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0016H Interrupt Source INTST1 INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTWT 0022H 0024H 0026H 0028H 002AH 002CH 002EH 00030H 0032H 0038H Vector Table Address 001CH 001EH 0020H
48
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
8.3 Context Switching
When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated
0000B <7> Transfer Register bank n (n = 0 to 7)
PC19 to PC16
Register bank n (0 to 7) A B X C R4 R6 VP UP D H E L <3> Switching of register bank (RBS0 to RBS2 n) <4> RSS 0 IE 0
PC15 to PC0
<2> Save (bits 8 through 11 of temporary register)
<6> Exchange
R5 R7
<5> Save
V U
Temporary register <1> Save
T W
PSW
8.4 Macro Service
This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service
Read CPU Memory Write Macro service controller
Write SFR Read
Internal bus
Data Sheet U12376EJ1V0DS00
49
PD784224, 784225, 784224Y, 784225Y
8.5 Application Example of Macro Service
(1) Transmission of serial interface
Transfer data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
TxD1, TxD2
Transmit shift register TXS1, TXS2 (SFR)
Transfer control
INTST1, INTST2
Each time macro service request INTST1 and INTST2 are generated, the next transmit data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has become empty), vectored interrupt request INTST1 and INTST2 are generated. (2) Reception of serial interface
Receive data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
Receive buffer register RXB1, RXB2 (SFR)
RxD1, RxD2
Receive shift register
Reception control
INTSR1, INTSR2
Each time macro service request INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR1 and INTSR2 are generated.
50
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
9. LOCAL BUS INTERFACE
The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbyte (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (Multiplexed bus)
PD784225
VDD1 SRAM CS Data bus OE WE I/O1 to I/O8 Address bus A0 to A19 Address latch
RD WR A8 to A19
ASTB
LE Q0 to Q7 D0 to D7 OE
AD0 to AD7
9.1 Memory Expansion
External program and data memory can be connected in two stages: 256 Kbytes and 1 Mbytes. To connect the external memory, ports 4 to 6 are used. The external memory is connected by using a time-division address/data bus. The number of ports used when the external memory is connected can be reduced in this mode.
9.2 Programmable Wait
Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active. In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time.
9.3 External Access Status Function
An active low external access status signal is output from the P37/EXA pin. This signal notifies other devices connected to the external bus of the external access status, to disable data output to the external bus from other devices, or enables reception. The external access status signal is output during external access.
Data Sheet U12376EJ1V0DS00
51
PD784224, 784225, 784224Y, 784225Y
10. STANDBY FUNCTION
This function is to reduce the power consumption of the chip, and can be used in the following modes: * HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. * IDLE mode : Stops the entire system with the oscillator continuing operation. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. * STOP mode : Stops the main system clock and thereby to stop all the internal operations of the chip. Consequently, the power consumption is minimized with only leakage current flowing. * Power-saving mode : The main system clock is stopped with the subsystem clock used as the system clock. The CPU can operate on the subsystem clock to reduce the current consumption. * Power-saving HALT mode : This is a standby function in the power-saving mode and stops the operation clock of the CPU, to reduce the power consumption of the entire system. * Power-saving IDLE mode : This is a standby function in the power-saving mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system. These modes are programmable. The macro service can be started from the HALT mode and power-saving HALT mode. After executing macro service processing, it returns to the HALT mode.
52
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Figure 10-1. Transition of Standby Status
Macro service
t es qu re sing ice es ice rv oc se pr erv ro one ro s ac M d of mac En d of En
e on d En Ma cro of
se
rvi
Powersaving HALT mode (standby) Interrupt request of masked interrupt
Power-saving HALT mode is set. Interrupt requestNote 1
ce
req
pr
oc es sin g ue st
Power-saving IDLE mode is set. PowerPowersaving mode saving IDLE (operation on NMI, INTP02 to INTP6 input, Note mode subsystem INTWT (standby) clock) Interrupt request of masked interrupt
Pow er-sa Norm ving HAL T mo al op de is erati se on is resto t. red.
NM Se ts ke I, I ID y r NT LE etu P0 rn m to od int IN e er TP ru 6i pt No n te pu 2 t, I End of oscilla NT tion stabiliza W tion time T
,
Se
ts
ST
OP
mo
de
STOP (standby)
Interrupt request of masked interrupt
IDLE (standby)
Interrupt request of masked interrupt
Interrupt request of masked interrupt
HALT (standby)
NM RE SE INT I, IN Ti WT TP0 np ,k ut to ey I ret NTP urn 6 i int npu err t, up N t ote
RE
SE
T
in
pu
t
2
Waits for oscillation stabilization
Notes 1. Only unmasked interrupt requests 2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87) Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode).
M ac En ro s er d of v on ice r e pr equ oc es es t sin g
R ES ET in pu t
RE
SE
T in
put
Normal operation (operation on main system clock)
Macro service request End of one processing End of macro service
Macro service
t es qu re t pt npu e ru i er T od Int SE T m RE AL H ts
Se
RE
T SE
in pu t
Data Sheet U12376EJ1V0DS00
53
PD784224, 784225, 784224Y, 784225Y
11. RESET FUNCTION
When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current consumption of the entire system can be reduced. When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 MHz) elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address set to the PC, and program execution is started from that branch address. Therefore, the program can be reset and started from any address. Figure 11-1. Oscillation of Main System Clock during Reset Period
Main system clock oscillator Oscillation is unconditionally stopped during rest period fCLK
RESET input Oscillation stabilization time
The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise. Figure 11-2. Accepting Reset Signal
Time until the clock starts oscillation Analog delay Oscillation stabilization time
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
54
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
12. ROM CORRECTION
ROM correction is a function to replace part of the program in the internal ROM with a program in the internal RAM. By using the ROM correction function, instruction bugs found in the internal ROM can be avoided or the flow of the program can be changed. ROM correction can be used at up to four places in the internal ROM (program). Figure 12-1. Block Diagram of ROM Correction
Program counter (PC)
Coincidence Comparator
Correction branch processing request signal (CALLT instruction)
Correction address pointer n
Correction address registers (CORAH, CORAL)
CORENn CORCHm ROM correction control register (CORC) Internal bus
Remark n = 0 to 3, m = 0 or 1
Data Sheet U12376EJ1V0DS00
55
PD784224, 784225, 784224Y, 784225Y
13. INSTRUCTION SET
(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 13-1. Instruction List by 8-Bit Addressing
Second Operand #byte A r r' First Operand A (MOV) ADD
Note 1
saddr saddr'
sfr
!addr16 !!addr24
mem [saddrp] [%saddrg]
r3 PSWL PSWH MOV
[WHL+] [WHL-]
n
NoneNote 2
(MOV) (XCH)
MOV XCH
(MOV)Note 6 (XCH)Note 6
MOV (XCH)
(MOV) (XCH)
MOV XCH ADDNote 1
(MOV) (XCH) (ADD)Note 1 ROR Note 3 MULU DIVUW INC DEC
(ADD)Note 1 (ADD)Note 1 (ADD)Note 1,6 (ADD)Note 1 ADDNote 1 r MOV ADD
Note 1
(MOV) (XCH)
MOV XCH
MOV XCH ADDNote 1
MOV XCH ADDNote 1
MOV XCH
(ADD)Note 1 ADDNote 1
saddr
MOV ADD
Note 1
(MOV) Note 6
MOV
MOV XCH ADDNote 1
INC DEC DBNZ PUSH POP CHKL CHKLA
(ADD)Note 1 ADDNote 1
sfr
MOV
MOV
MOV
ADDNote 1 (ADD)Note 1 ADDNote 1
!addr16 !!addr24 mem [saddrp] [%saddrg] mem3
MOV
(MOV) ADDNote 1 MOV ADDNote 1
MOV
ROR4 ROL4
r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-]
MOV
MOV
DBNZ MOV (MOV) (ADD)
Note 1
MOVBKNote 5
MOVMNote 4
Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short.
56
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 13-2. Instruction List by 16-Bit Addressing
Second Operand #word AX rp rp' First Operand AX (MOVW) ADDW
Note 1
saddrp saddrp'
sfrp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
NoneNote 2
(MOVW) (XCHW)
(MOVW) (MOVW) (XCHW) (XCHW)
Note 3
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
Note 3
(ADD)Note 1 (ADDW)Note 1 (ADDW)Note 1,3 (ADDW)Note 1 rp MOVW ADDW
Note 1
(MOVW) (XCHW) (ADDW)
Note 1
MOVW XCHW ADDW
Note 1
MOVW XCHW ADDW
Note 1
MOVW XCHW ADDW
Note 1
MOVW
SHRW SHLW
MULW Note 4 INCW DECW INCW DECW
saddrp
MOVW (MOVW)Note 3 MOVW ADDW
Note 1
MOVW XCHW ADDWNote 1
(ADDW)
Note 1
ADDW
Note 1
sfrp
MOVW
MOVW
MOVW
PUSH POP MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW.
Data Sheet U12376EJ1V0DS00
57
PD784224, 784225, 784224Y, 784225Y
(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 13-3. Instruction List by 24-Bit Addressing
Second Operand #imm24 WHL rg rg' First Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP None Note
Note Either the second operand is not used, or the second operand is not an operand address.
58
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 13-4. Bit Manipulation Instructions
Second Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr. bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 None Note
Note Either the second operand is not used, or the second operand is not an operand address.
Data Sheet U12376EJ1V0DS00
59
PD784224, 784225, 784224Y, 784225Y
(5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 13-5. Call and Return/Branch Instructions
Operand of Instruction Address Basic instruction BCNote BR CALL BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
60
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
14. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD0 AVDD AVSS AVREF1 Input voltage Analog input voltage Output voltage Output current, low VI VAN VO IOL Per pin Total of all pins Output current, high IOH Per pin Total of all pins Operating ambient temperature Storage temperature TA Analog input pin D/A converter reference voltage input Conditions Ratings -0.3 to +6.5 -0.3 to VDD0 + 0.3 -0.3 to VSS0 + 0.3 -0.3 to VDD0 + 0.3 -0.3 to VDD0 + 0.3 AVSS - 0.3 to AVREF1 + 0.3 -0.3 to VDD + 0.3 15 100 -10 -40 -40 to +85 -65 to +150 Unit V V V V V V V mA mA mA mA C C
Tstg
Caution
Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values.
Data Sheet U12376EJ1V0DS00
61
PD784224, 784225, 784224Y, 784225Y
Operating Conditions * Operating ambient temperature (TA): -40C to +85C * Power supply voltage and clock cycle time: see Figure 14-1 * Operating voltage when the subsystem clock is operating: VDD = 1.8 to 5.5 V Figure 14-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
500
Clock cycle time tCYK [ns]
400 Guaranteed operation range
320 300
200 160 100 80
0 0 1 1.8 2 2.7 3 Supply voltage [V] 4 4.5 5 5.5 6
Capacitance (TA = 25C, VDD = VDD0 = VDD1 = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
62
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Main System Clock Oscillator Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1)
Resonator Recommended Circuit Ceramic resonator or crystal resonator Parameter Oscillation frequency (fX) Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V MIN. 2 2 2 2 TYP. MAX. 12.5 6.25 3.125 2 Unit MHz
X2
X1 VSS
External clock
X1 input frequency (fX)
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V
2 2 2 2 15
12.5 6.25 3.125 2 250
MHz
X2
X1
X1 input high-/lowlevel width (tWXH, tWXL)
1.8 V VDD < 2.0 V
ns
PD74HCU04
X1 input rising/falling time (tXR, tXF)
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V
0 0 0 0
5 10 20 30
ns
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U12376EJ1V0DS00
63
PD784224, 784225, 784224Y, 784225Y
Subsystem Clock Oscillator Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1)
Resonator Recommended Circuit Crystal resonator
VSS XT2 XT1
Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote
Conditions
MIN. 32
TYP. 32.768 1.2
MAX. 35 2 10
Unit kHz s
4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V
External clock
XT2
XT1
XT1 input frequency (fXT) XT1 input high-/low-level width (tXTH, tXTL)
32 14.3
35 15.6
kHz
s
PD74HCU04
Note Time required to stabilize oscillation after applying supply voltage (VDD). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
64
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
DC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (1/2)
Parameter Input voltage, low Symbol VIL1 Note 1 Conditions 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIL2 P00 to P05, P20, P22, P33, P34, P70, P72, RESET VIL4 P10 to P17, P130, P131 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIL5 X1, X2, XT1, XT2 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIL6 P25, P27 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V Input voltage, high VIH1 Note 1 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIH2 P00 to P05, P20, P22, P33, P34, P70, P72, RESET VIH4 P10 to P17, P130, P131 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIH5 X1, X2, XT1, XT2 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V VIH6 P25, P27 2.2 V VDD 5.5 V 1.8 V VDD < 2.2 V Output voltage, low VOL1 For pins other than P40 to P47, P50 to P57, IOL = 1.6 mANote 2 P40 to P47, P50 to P57 IOL = 8 mANote 2 VOL2 Output voltage, high VOH1 IOL = 400 ANote 2 IOH = -1 mANote 2 4.5 V VDD 5.5 V VDD - 1.0 VDD - 0.5 Except X1, X2, XT1, XT2 X1, X2, XT1, XT2 VIN = VDD0 Except X1, X2, XT1, XT2 X1, X2, XT1, XT2 VOUT = 0 V -3 -20 3 4.5 V VDD 5.5 V MIN. 0 0 0 0 0 0 0 0 0 0 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD TYP. MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 0.4 V V V V V V V V V V Unit V
4.5 V VDD 5.5 V
1.0
V
0.5
V V V
IOH = -100 Input leakage current, low ILIL1 VIN = 0 V
ANote 2
A A A A A A
ILIL2 Input leakage current, high ILIH1
ILIH2 Output leakage current, low Output leakage current, high ILOL1
20 -3
ILOH1
VOUT = VDD
3
Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin
Data Sheet U12376EJ1V0DS00
65
PD784224, 784225, 784224Y, 784225Y
DC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (2/2)
Parameter Supply voltage Symbol IDD1 Operation mode Conditions fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 10% IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 10% IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V 10% fXX = 6 MHz, VDD = 3.0 V 10% fXX = 2 MHz, VDD = 2.0 V 10% IDD4 Operation modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, VDD = 2.0 V 10% IDD5 HALT modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, VDD = 2.0 V 10% IDD6 IDLE modeNote fXX = 32 kHz, VDD = 5.0 V 10% fXX = 32 kHz, VDD = 3.0 V 10% fXX = 32 kHz, VDD = 2.0 V 10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode VDD = 2.0 V 10% VDD = 5.0 V 10% Pull-up resistor RL VIN = 0 V 10 1.8 2 10 30 MIN. TYP. 17 5 2 7 2 0.5 1 0.4 0.2 80 60 30 60 20 10 50 15 5 MAX. 40 17 8 20 8 3.5 2.5 1.3 0.9 200 110 100 160 80 70 150 70 60 5.5 10 50 100 Unit mA mA mA mA mA mA mA mA mA
A A A A A A A A A
V
A A
k
Note When main system clock is stopped. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
66
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
AC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (1) Read/write operation (1/3)
Parameter Cycle time Symbol tCYK Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V Address setup time (to ASTB) tSAST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Address hold time (from ASTB) tHSTLA VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% ASTB high-level width tWSTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Address hold time (from RD) tHRA VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from address to RD tDAR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Address float time (from RD) tFAR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Data input time from address tDAID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Data input time from ASTB tDSTID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Data input time from RD tDRID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% MIN. 80 160 320 500 (0.5 + a) T - 20 (0.5 + a) T - 40 (0.5 + a) T - 80 0.5T - 19 0.5T - 24 0.5T - 34 (0.5 + a) T - 17 (0.5 + a) T - 40 (0.5 + a) T - 110 0.5T - 14 0.5T - 14 0.5T - 14 (1 + a) T - 24 (1 + a) T - 35 (1 + a) T - 80 0 0 0 (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 (2.5 + a + n) T - 120 (2 + n) T - 35 (2 + n) T - 50 (2 + n) T - 80 (1.5 + n) T - 40 (1.5 + n) T - 50 (1.5 + n) T - 90 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U12376EJ1V0DS00
67
PD784224, 784225, 784224Y, 784225Y
AC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (1) Read/write operation (2/3)
Parameter Delay time from ASTB to RD Symbol tDSTR Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Data hold time (from RD) tHRID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Address active time from RD tDRA VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from RD to ASTB tDRST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% RD low-level width tWRL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from address to WR tDAW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Address hold time (from WR) tHRD VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from ASTB to data output tDSTOD VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WR to data output tDWOD VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from ASTB to WR tDSTW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Data setup time (to WR) tSODWR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% 0.5T - 9 0.5T - 9 0.5T - 20 (1.5 + n) T - 20 (1.5 + n) T - 25 (1.5 + n) T - 70 MIN. 0.5T - 9 0.5T - 9 0.5T - 20 0 0 0 0.5T - 2 0.5T - 12 0.5T - 35 0.5T - 9 0.5T - 9 0.5T - 40 (1.5 + n) T - 25 (1.5 + n) T - 30 (1.5 + n) T - 25 (1 + a) T - 24 (1 + a) T - 34 (1 + a) T - 70 0.5T - 14 0.5T - 14 0.5T - 14 0.5T + 15 0.5T + 30 0.5T + 240 0.5T - 30 0.5T - 30 0.5T - 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
68
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
AC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (1) Read/write operation (3/3)
Parameter Data hold time (from WR) Symbol tHWOD Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WR to ASTB tDWST VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% WR low-level width tWWL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% MIN. 0.5T - 14 0.5T - 14 0.5T - 50 0.5T - 9 0.5T - 9 0.5T - 30 (1.5 + n) T - 25 (1.5 + n) T - 30 (1.5 + n) T - 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U12376EJ1V0DS00
69
PD784224, 784225, 784224Y, 784225Y
AC Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (2) External wait timing (1/2)
Parameter Input time from address to WAIT Symbol tDAWT Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Input time from ASTB to WAIT tDSTWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Hold time from ASTB to WAIT tHSTWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from ASTB to WAIT tDSTWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Input time from RD to WAIT tDRWTL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Hold time from RD to WAIT tHRWT VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from RD to WAIT tDRWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Input time from WAIT to data tDWTID VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WAIT to RD tDWTR VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WAIT to WR tDWTW VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WR to WAIT tDWWTL VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% 0.5T 0.5T 0.5T + 5 0.5T 0.5T 0.5T + 5 T - 40 T - 60 T - 90 nT + 5 nT + 10 nT + 30 (1 + n) T - 40 (1 + n) T - 60 (1 + n) T - 90 0.5T - 5 0.5T - 10 0.5T - 30 (0.5 + n) T + 5 (0.5 + n) T + 10 (0.5 + n) T + 30 (1.5 + n) T - 40 (1.5 + n) T - 60 (1.5 + n) T - 90 T - 40 T - 60 T - 70 MIN. TYP. MAX. (2 + a) T - 40 (2 + a) T - 60 (2 + a) T - 300 1.5T - 40 1.5T - 60 1.5T - 260 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
70
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(2) External wait timing (2/2)
Parameter Hold time from WR to WAIT Symbol tHWWT Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% Delay time from WR to WAIT tDWWTH VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% MIN. nT + 5 nT + 10 nT + 30 (1 + n) T - 40 (1 + n) T - 60 (1 + n) T - 90 TYP. MAX. Unit ns ns ns ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
Data Sheet U12376EJ1V0DS00
71
PD784224, 784225, 784224Y, 784225Y
Serial Operation (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (a) 3-wire serial I/O mode (SCK: Internal clock output)
Parameter SCK cycle time Symbol tKCY1 2.7 V VDD 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width SI setup time (to SCK) tKH1, tKL1 tSIK1 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 350 1,500 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI1 tKSO1 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
(b) 3-wire serial I/O mode (SCK: External clock input)
Parameter SCK cycle time Symbol tKCY2 2.7 V VDD 5.5 V Conditions MIN. 800 3,200 SCK high-/low-level width SI setup time (to SCK) tKH2 tKL2 tSIK2 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 400 1,600 10 30 SI hold time (from SCK) SO output delay time (from SCK) tKSI2 tKSO2 40 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns
(c) UART mode
Parameter ASCK cycle time Symbol tKCY3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Conditions MIN. 417 833 1,667 ASCK high-/low-level width tKH3 tKL3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 208 416 833 TYP. MAX. Unit ns ns ns ns ns ns
72
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(d) I2C bus mode (PD784225Y only)
Parameter Symbol MIN. SCL0 clock frequency Bus free time (between stop and start conditions) Hold timeNote1 Low-level width of SCL0 clock High-level width of SCL0 clock Setup time of start/restart conditions Data hold When using time CBUS-compatible master When using I2C bus Data setup time Rising time of SDA0 and SCL0 signals Falling time of SDA0 and SCL0 signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line tSU : STO tSP 4.0 - - - - 0.6 0 - - 50 tSU : DAT tR fCLK tBUF 0 4.7 Standard Mode MAX. 100 - - - - - - High-Speed Mode MIN. 0 1.3 MAX. 400 - - - - - - kHz Unit
s s s s s s
tHD : STA tLOW
4.0 4.7
0.6 1.3
tHIGH
4.0
0.6
tSU : STA
4.7
0.6 -
tHD : DAT
5.0
0Note 2
- - 1,000
0Note 2 100Note 4 20 + 0.1CbNote 5 20 + 0.1CbNote 5
0.9Note 3 - 300
s
ns ns
250 - -
tF
300
300
ns
s
ns
Cb
400
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold time tHD : DAT needs to be satisfied. 4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low-level hold time tSU : DAT 250 ns * If the device extends the SCL0 signal low-level hold time Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : DAT = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification) 5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U12376EJ1V0DS00
73
PD784224, 784225, 784224Y, 784225Y
Other Operations (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)
Parameter NMI high-/low-level width INTP input high-/lowlevel width RESET high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 to INTP6 Conditions MIN. 10 TYP. MAX. Unit
s
ns
100
10
s
Clock Output Operation (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)
Parameter PCL cycle time PCL high-/low-level width PCL rising/falling time Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 4.5 V VDD 5.5 V, nT 4.5 V VDD 5.5 V, 0.5T - 10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V MIN. 80 30 TYP. MAX. 31,250 15,615 Unit ns ns
5 10 20
ns ns ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) n: Divided frequency ratio set by software in the CPU * When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 * When using the subsystem clock: n = 1
74
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
A/D Converter Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)
Parameter Resolution Overall errorNote 6.25 MHz < fXX 12.5 MHz, 4.5 V VDD 5.5 V, AVDD = VDD0 3.125 MHz < fXX 6.25 MHz, 2.7 V VDD 5.5 V, AVDD = VDD0 2 MHz < fXX 3.125 MHz, 2.0 V VDD 5.5 V, AVDD = VDD0 fXX = 2 MHz, 1.8 V VDD 5.5 V AVDD = VDD0 Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVDD and AVSS tCONV tSAMP VIAN AVDD RAVREF0 A/D conversion is not performed 14 24/fXX AVSS VDD VDD 40 AVDD VDD Symbol Conditions MIN. 8 TYP. 8 MAX. 8 Unit bit
1.2 %FSR 1.2 %FSR 1.6 %FSR 1.6 %FSR
144
s s
V V k
Note Excludes quantization error (0.2%FSR). Remark FSR: Full-scale range D/A Converter Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)
Parameter Resolution Overall errorNote 2.0 V VDD 5.5 V R = 10 M, 2.0 V AVREF1 5.5 V 1.8 V VDD 2.0 V R = 10 M, 1.8 V AVREF1 5.5 V Settling time Load conditions: C = 30 pF 4.5 V AVREF1 5.5 V 2.7 V AVREF1 < 4.5 V 1.8 V AVREF1 < 2.7 V Output resistance Reference voltage AVREF1 current RO AVREF1 AIREF1 For only 1 channel DACS0, 1 = 55H 1.8 8 VDD0 2.5 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 Unit bit
0.6 %FSR 1.2 %FSR
10 15 20
s s s
k V mA
Note Excludes quantization error (0.2%FSR). Remark FSR: Full-scale range
Data Sheet U12376EJ1V0DS00
75
PD784224, 784225, 784224Y, 784225Y
Data Retention Characteristics (TA = -40C to +85C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = 5.0 V 10% VDDDR = 2.0 V 10% VDD rise time VDD fall time VDD hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage VIL VIH tRVD tFVD tHVD 200 200 0 Conditions MIN. 1.8 10 2 TYP. MAX. 5.5 50 10 Unit V
A A s s
ms
tDREL
0
ms
tWAIT
Crystal resonator Ceramic resonator RESET, P00/INTP0 to P06/INTP6
30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms V V
AC Timing Measurement Points
VDD - 1 V
0.8VDD or 1.8 V 0.8 V
Points of measurement
0.8VDD or 1.8 V 0.8 V
0.45 V
76
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Timing Waveform (1) Read operation
(CLK) tCYK
A0 to A7 (Output)
Lower address
Lower address
A8 to A19 (Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFAR Hi-Z
Higher address
tDSTID AD0 to AD7 (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
RD (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Data Sheet U12376EJ1V0DS00
77
PD784224, 784225, 784224Y, 784225Y
(2) Write operation
(CLK) tCYK
A0 to A7 (Output)
Lower address
Lower address
A8 to A19 (Output) tDAID
Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFAR tSODWR Hi-Z
Higher address
tDSTOD AD0 to AD7 (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
WR (Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
78
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Serial Operation (1) 3-wire serial I/O mode
tKCY1, 2 tKH1, 2 tKL1, 2 SCK tKSO1, 2 tKSI1, 2 tSIK1, 2 SI/SO
(2) UART mode
tKCY3 tKH3 ASCK tKL3
(3) I2C bus mode (PD784255Y Subseries only)
tLOW SCL0 tHD : DAT tHD : STA tF tR
tHIGH tSU : DAT
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U12376EJ1V0DS00
79
PD784224, 784225, 784224Y, 784225Y
Clock Output Timing
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH tWNIL
NMI
tWITH
tWITL
INTP0 to INTP6
Reset Input Timing
tWRSH tWRSL
RESET
80
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Clock Timing
tWXH tWXL
X1 tXR 1/fX tXF
tXTH
tXTL
XT1
1/fXT
Data Retention Characteristics
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Cleared by falling edge)
NMI (Cleared by rising edge)
Data Sheet U12376EJ1V0DS00
81
PD784224, 784225, 784224Y, 784225Y
15. PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
82
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D P T
80 1 F G H I
M
21 20 Q J
R
L U
K S N
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
S
M
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1
Data Sheet U12376EJ1V0DS00
83
PD784224, 784225, 784224Y, 784225Y
16. RECOMMENDED SOLDERING CONDITIONS
The PD784225 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Caution Soldering conditions for the PD784224GC-xxx-8BT, PD784225YGC-xxx-8BT, and PD784225YGKxxx-9EU are undetermined because these products are under development. Table 16-1. Soldering Conditions for Surface Mount Type (1) PD784225GC-xxx-8BT: 80-pin plastic QFP (14 x 14 mm)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours)
VPS
VP15-00-2
Wave soldering
--
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
--
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
(2) PD784224GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (14 x 20 mm)
PD784225GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (14 x 20 mm)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Wave soldering
--
Partial heating
--
Caution
Do not use different soldering methods together (except for partial heating).
84
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD784225. Also see (5). (1) Language Processing Software
RA78K4 CC78K4 DF784225 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file common to PD784225, 784225Y Subseries C compiler library source file common to 78K/IV Series
(2) Flash Memory Writing Tools
Flashpro II (Part No.: FL-PR2), Flashpro III (Part No.: FL-PR3, PG-FP3) FA-80GC FA-80GK Dedicated flash programmer for microcontroller incorporating flash memory
Adapter for writing 80-pin plastic QFP (GC-8BT type) flash memory. Adapter for writing 80-pin plastic LQFP (GK-BE9 type) flash memory.
(3) Debugging Tools * When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) PC card and cable when notebook PC is used as host machine (PCMCIA socket supported) Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported) Interface adapter when using PC that incorporates PCI bus as host machine Emulation board to emulate PD784225, 784225Y Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file common to PD784225, 784225Y Subseries
IE-70000-CD-IF-A IE-70000-PC-IF-C
IE-70000-PCI-IF IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW
ID78K4-NS SM78K4 DF784225
Data Sheet U12376EJ1V0DS00
85
PD784224, 784225, 784224Y, 784225Y
* When IE-784000-R in-circuit emulator is used
IE-784000-R IE-70000-98-IF-C In-circuit emulator common to 78K/IV Series Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) Interface adapter when using PC that incorporates PCI bus as host machine Interface adapter and cable used when EWS is used as host machine Emulation board to emulate PD784225, 784225Y Subseries
IE-70000-PC-IF-C
IE-70000-PCI-IF IE-78000-R-SV3 IE-784225-NS-EM1 IE-784218-R-EM1 IE-784000-R-EM IE-78K4-R-EX3
Emulation board common to 78K/IV Series Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE784000-R. Not necessary when IE-784216-R-EM1 is used. Emulation probe for 100-pin plastic QFP (GF-3BA type) Emulation probe for 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file common to PD784225, 784225Y Subseries
EP-78064GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW
ID78K4 SM78K4 DF784225
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series
86
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
(5) Cautions on Using Development Tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784225. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218. * The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). * The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) * For third-party development tools, see the 78K/IV Series Selection Guide (U13355E). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note
PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows]
Note Note
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM]
-
-
Note DOS-based software
Data Sheet U12376EJ1V0DS00
87
PD784224, 784225, 784224Y, 784225Y
APPENDIX B. RELATED DOCUMENTS
Documents related to device
Document Name Japanese Document No. English This document Planned Planned - U10905E - - U10095E
PD784224, 784225, 784224Y, 784225Y Data Sheet PD78F4225, 78F4225Y Data Sheet PD784225, 784225Y Subseries User's Manual - Hardware PD784225Y Subseries Special Function Register Table
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U12376J U12377J Planned Planned U10905J U10594J U10595J U10095J
Documents related to development tools (User's Manuals)
Document Name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 C Compiler Operation Language IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator - Windows Base SM78K Series System Simulator Reference External component user open interface specification Reference Reference Reference U11334J U11162J U11743J U11572J U11571J U13356J U12903J U12155J U13742J EEU-934 U10093J U10092J Document No. English U11334E U11162E U11743E U11572E U11571E U13356E U12903E U12155E U13742E EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger - PC Base ID78K4 Integrated Debugger - Windows Base ID78K4 Integrated Debugger - HP-UX, SunOS, NEWS-OS Base
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing.
88
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Documents related to embedded software (User's Manual)
Document Name Japanese 78K/IV Series Real-Time OS Basics Installation Debugger 78K/IV Series OS MX78K4 Basics U10603J U10604J U10364J U11779J Document No. English U10603E U10604E - -
Other documents
Document Name Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide for Products Related to Micro-Computer: Other Companies X13769X C10535J C11531J C10983J C11892J C10535E C11531E C10983E C11892E Document No. English
C12769J U11416J
MEI-1202 -
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing.
Data Sheet U12376EJ1V0DS00
89
PD784224, 784225, 784224Y, 784225Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
90
Data Sheet U12376EJ1V0DS00
PD784224, 784225, 784224Y, 784225Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12376EJ1V0DS00
91
PD784224, 784225, 784224Y, 784225Y
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7D 98. 12
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